1. Field
The following description relates to a transactional memory, and more particularly, to a hardware based unbounded transactional memory system.
2. Description of the Related Art
A conventional processor generally includes several cores integrated onto a single chip, and it is expected that an ever increasing number of cores will be mounted onto single chips for a processor. Due to such trend, the importance of parallel processing has been increasingly recognized.
In a multi-core environment, locks are used as a solution for synchronization problems. Locks allow access to a shared memory in a mutually exclusive way. However, the use of locks may result in various drawbacks such as deadlock, convoy effect, priority inversion, and the like. Deadlock is a failure or inability to proceed due to two processors both requiring a response from the other before completing an operation. Priority inversion occurs when a high priority task is indirectly preempted by a medium priority task effectively “inverting” the relative priorities of the two tasks. The convoy effect is the slow down of instructions due to queuing caused by slow processing. In addition, it is difficult to implement a fine-grain lock for efficiently utilizing the locks.
A transactional memory has been proposed to facilitate parallel programming. Generally, a “transactional memory” refers to a synchronization model that allows a number of threads to simultaneously access shared resources, such as a data structure stored in a memory, without acquiring locks, as long as access conflict does not occur. For example, the threads may simultaneously access shared resources as long as the threads access different parts of the shared resources. Recently, to make the hardware transactional memory system more useful, an unbounded transactional memory has been introduced, which enables the management of data larger than a cache size.